The packaging of semiconductor components such as power semiconductor devices involves a number of design challenges. Such challenges include cost, heat dissipation, device protection, size, performance, and reliability among others. Examples of prior art power packages that have been developed and improved upon to address such issues include the TO-220, TO-218, CASE 77, TO-247, Dpak, D2pak, D3pak, quad flat pack no-lead (QFN), quad flat pack (QFP), small outline (SOP) packages among others.
In a typical power semiconductor package, a semiconductor chip or device is attached to a conductive lead frame having an attach paddle and conductive leads. Input/output pads on the semiconductor chip are then coupled to the leads using conductive wires. The semiconductor chip and portions of the metal lead frame are then encapsulated with an epoxy mold compound, which functions to protect the device. Portions of the conductive leads are left exposed or unencapsulated so that the packaged device may be attached to a next level of assembly such as a printed circuit board. In the prior art packages listed above, the major or main current carrying surfaces of the semiconductor device are parallel to the next level of assembly when attached thereto.
Although advances have been made in semiconductor packaging, the electronics industry still demands smaller, more cost effective, and more reliable packaged semiconductor devices. This includes packaged devices that have enhanced thermal performance, and that are adaptable to various electrical configurations.
Accordingly, a need exists for a package structure and method of manufacture that addresses these demands as well as others.